This section provides background information related to the present disclosure which is not necessarily prior art.
FIG. 1 illustrates an exemplary embodiment of the semiconductor light emitting device chip disclosed in U.S. Pat. No. 7,262,436, which includes a substrate 100, an n-type semiconductor layer 300 grown on the substrate 100, an active layer 400 grown on the n-type semiconductor layer 300, a p-type semiconductor layer 500 grown on the active layer 400, three-layer electrodes 901, 902 and 903 which are formed on the p-type semiconductor layer 500 and serve to reflect light towards the substrate 100, and an electrode 800 which is formed on an exposed etched portion of the n-type (first) semiconductor layer 300 and serves as a bonding pad. The electrode 901 serves as a reflective film, the electrode 902 serves as a barrier, and the electrode 903 serves to facilitate bonding with an external electrode. This semiconductor light emitting chip with the above structure has the electrode 800 and the electrode 903 being directly connected to an SMD type package, PCB (Printed Circuit Board), COB (Chip-on Board), submount (without wire-bonding) or the like, and is called a flip chip.
FIG. 2 illustrates an exemplary embodiment of the semiconductor LED chip disclosed in JP Laid-Open Pub. No. 2006-120913, which includes a substrate 100, a buffer layer 200 grown on the substrate 100, an n-type semiconductor layer 300 grown on the buffer layer 200, an active layer 400 grown on the n-type semiconductor layer 300, a p-type semiconductor layer 500 grown on the active layer 400, a light transmitting conductive layer 600 which is formed on the p-type semiconductor layer 500 and serves to spread current, a p-side bonding pad 700 formed on the light transmitting conductive film 600, and an n-side bonding pad 800 formed on an exposed etched portion of the n-type semiconductor layer 300. In addition, a DBR (Distributed Bragg Reflector) 900 and a metal reflective film 904 are formed on the light transmitting conductive film 600. The n-type semiconductor layer 300 and the p-type semiconductor layer 500 each includes a plurality of layers, and the positions of the n-type and p-type semiconductor layers 300 and 500 may be exchanged. Although not desired, the buffer layer 200 and the light transmitting conductive film 600 may be omitted.
FIG. 3 illustrates an exemplary embodiment of the semiconductor LED chip disclosed in PCT Pub. No. WO2014/014298, which includes a substrate 100, a buffer layer 200 grown on the substrate 100, an n-type semiconductor layer 300 grown on the buffer layer 200, an active layer 400 grown on the n-type semiconductor layer 300, a p-type semiconductor layer 500 grown on the active layer 400, a light transmitting conductive film 600 which is formed on the p-type semiconductor layer 500 and serves to spread current, a non-conductive reflective film 900 (e.g., DBR) which is formed on the light transmitting conductive film 600 and serves to reflect light generated by the active layer 400, and electrodes 700 and 800 formed on the non-conductive reflective film 900. The electrode 700 and the electrode 800 are in electrical communication with the n-type semiconductor 300 and the p-type semiconductor layer 500 through a conducting part 710 and a conducting part 810, respectively.
FIG. 4 illustrates an exemplary embodiment of the semiconductor light emitting device disclosed in JP Laid-Open Pub. No. 2001-358371, which includes a substrate 100, an n-type semiconductor layer 300 grown on the substrate 100, an active layer 400 grown on the n-type semiconductor layer 300, a p-type semiconductor layer 500 grown on the active layer 400, a p-side electrode 700 formed on the p-type semiconductor layer 500, and an n-side electrode 800 formed on an exposed etched portion of the n-type semiconductor layer 300. An insulating film 9 is provided between the electrode 700 and the electrode 800. This semiconductor light emitting device includes, in addition to a semiconductor LED chip, a body 1, a read frame 2, 3 formed on the body 1, a mold 5 forming a cavity 4 on the lead frame 2, 3, and an encapsulant 1000 encompassing the semiconductor LED chip. The encapsulant 1000 may include a phosphor, a light scattering agent, and the like. The electrodes 700 and 800 are fixed to the lead frame 2 and 3 by means of a bonding layer 7. While the electrodes 700 and 800 and the lead frames 2 and 3 can be electrically connected by bonding with a stud bump or conductive paste, or by soldering or eutectic bonding, the bonding methods are not particularly limited thereto.
FIG. 5 illustrates an exemplary embodiment of a semiconductor light emitting device in the prior art, in which a substrate 100 of a semiconductor LED chip is electrically connected to a lead frame 3 by means of a wire 8, while the substrate is already being fixed to a lead frame 2. When wire bonding is applied as in this case and heat is produced within the device, the presence of the substrate 100 between a plurality of semiconductor layers 300, 400 and 500 and the lead frames 2 and 3 can protect the plurality of semiconductor layers 300, 400 and 500 from cracking or breaking, even if those semiconductor layers 300, 400 and 500 and the metallic lead frames 2 and 3 exhibit different thermal expansion behaviors. Such a chip is generally referred to as a lateral chip. For instance, for a Group-III nitride semiconductor light emitting device, an overall thickness of the plurality of semiconductor layers 300, 400 and 500 is typically not greater than 10 μm, and a thickness of the substrate 100 (e.g., sapphire substrate) ranges from 80 to 150 μm.
Referring again to FIG. 4, when the semiconductor LED chip is a flip chip bonded, the plurality of semiconductor layers 300, 400 and 500 and the lead frames 2 and 3 are arranged directly facing each other, and if the metallic lead frames 2 and 3 expand due to heat being generated, those semiconductor layers 300, 400 and 500 are highly likely to crack or break. Considering that there has been an increasing demand for flip chips operable with low current, instead of lateral chips, over a broad range of applications, the risk of the semiconductor layers 300, 400 and 500 being cracked or broken will increase as more heat is generated within a device that has a high-current (i.e. high-power) chip.